1. Technical Field
The present invention generally relates to a Radio Frequency Identification (RFID) device having a nonvolatile ferroelectric memory, and also to a method of supplying a high voltage only to a memory cell array area of a memory in the RFID device and a power voltage to peripheral areas to reduce power consumption.
2. Description of the Related Art
Generally, a ferroelectric random access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’) and conserves data even after the power is turned off.
A FeRAM may have a structure similar to a DRAM but includes capacitors made of a ferroelectric material, which has a high residual polarization characteristic such that data are not deleted even after an electric field is removed.
FIG. 1 is a diagram illustrating a conventional RFID device including a FeRAM.
The conventional RFID includes an antenna 10, an analog block 20, a digital block 30 and a memory 40.
The antenna 10 transmits and receives radio frequency signals to an external reader or from an external writer.
The analog block 20 includes a voltage multiplier 21, a voltage limiter 22, a modulator 23, a demodulator 24, a voltage doubler 25, a power-on reset unit 26 and a clock generating unit 27. The voltage multiplier 21 generates a power voltage VDD for the RFID device in response to the radio frequency signal received from the antenna 10. The voltage limiter 22 limits a voltage of the radio frequency signal received from the antenna 10. The modulator 23 modulates a response signal Response received from the digital block 20 and to be transmitted to the antenna 10. The demodulator 24 detects an operation command signal CMD within the radio frequency signal received from the antenna 10 and outputs the command signal CMD to the digital block 30. The voltage doubler 25 boosts the power voltage VDD provided by the voltage multiplier 21 to a boosted voltage VDD2, which has a swing width twice that of the power voltage VDD, and provides the boosted voltage VDD2 to the memory 40. The power-on reset unit 26 senses the power voltage VDD provided by the voltage multiplier 21 and outputs a power-on reset signal POR to control a reset operation of the digital block 30. The clock generating unit 27 generates a clock signal CLK.
The digital block 30 receives the power voltage VDD, the power-on reset signal POR, the clock signal CLK, and the command signal CMD from the analog block 20, and outputs the response signal Response to the analog block 20. The digital block 30 outputs an address ADD, data I/O, a control signal CTR, and the clock signal CLK to the memory 40.
The memory 40 has a plurality of memory cells each including a nonvolatile ferroelectric capacitor.
In the RFID device, the power source of the antenna is small. However, the RFID device consumes a significant amount of power. As a result, the output voltage VDD of the voltage multiplier 21 is very low.
In the conventional RFID device, the analog block 20 and the digital block 30 can be driven by the low voltage VDD while the memory 40 requires the high voltage VDD2. In addition, the memory 40 has a memory cell array area and a peripheral area. The boosted voltage VDD2 supplied from the voltage doubler 25 of FIG. 1 is required for the memory cell array area, and the peripheral area can be driven by a voltage lower than the boosted voltage VDD2. However, the boosted voltage VDD2 is supplied to all areas of the memory 40, which cause unnecessary power consumption.